Random Access Memory (RAM) is a memory which can be written to and read from with the capability for direct random access to addressed memory cells. One preferred, but not exclusive, field of application of the invention is dynamic RAMs (DRAMS), in particular “synchronous” dynamic RAMs (SDRAMS), as are used as main memories or graphics memories in computers.
A RAM module is normally integrated on a semiconductor chip and contains a large number of memory cells, which are arranged in the form of a matrix in rows and columns and are generally distributed over a plurality of individually addressable banks. The chip has a plurality of external connections (also referred to in the following text as “pins”), including address pins for application of the information for the addressing of the respective memory cells to be addressed, data pins, including a strobe pin, for inputting and outputting the memory data to be written to and read from the addressed memory cells with an accompanying strobe signal, and instruction pins for application of instructions for controlling the operation of the memory. During operation, the RAM module is connected via the pins that have been mentioned and associated connecting lines to corresponding pins of a control module (“controller”), which sends the memory data to be written and receives the data that has been read, and also sends the address information as well as the control instructions.
The pins (data pins and strobe pin) which are used for data transmission are a component of a bidirectional “data interface” both at the controller and at the RAM module, which data interface also contains output drivers (Off-Chip Driver OCD) for amplification of the signals to be transmitted and reception drivers (Off-Chip Receiver OCR) for amplification of the received signals.
In order to make the RAM module flexible in terms of its options for use, that is to say to make it possible to match it to different types of use and different environments, means are normally provided in order to set various state variables, which are in this case referred to as “operating parameters” or “parameters”, for short, as desired. These “mode” settings are normally made during an operating interval that is reserved for this purpose, for example in the initialization phase whenever the module is started up, by the controller, which for this purpose sends the required mode information to the module, where it is stored in a mode register. The content of the mode register then governs the values of the said parameters for subsequent operation during use of the module.
In order to store information in the mode register, the controller sends an instruction MRS (“Set Mode Register”) in the form of a specific pattern of parallel bits to the instruction connections of the RAM module, and at the same time sends the mode information, likewise as a pattern of parallel bits, to other existing connections of the module. Since no memory data is transmitted between the RAM module and the controller and no memory cells are addressed either during the mode setting interval, the address connections as well as the data connections can be used for inputting the mode information during this time. A specific set of address connections is normally selected in order to carry out the role of mode information connections during the mode setting interval. Each of these dedicated connections is connected to the data input of one, and only one, cell, which is associated with it, in the mode register, whose set input is triggered by the adjustment instruction MRS.
The size of the mode register (the number of cells) is thus limited to the number of setting information connections. This restricts the adjustment capabilities, to be precise both in terms of the numbers of parameters which can be adjusted and in terms of the variation width or the fineness of the adjustment of the parameter values. For this reason, additional mode settings, which go beyond the capacity of the mode register, must be provided in a different way. It is thus advantageous, for example, for drivers in the data interface of the RAM module each to have the capability to set one or more operating parameters relatively finely. This applies in particular to the output drivers.
One important parameter, for example, of the output drivers in the data interface of the RAM module is the current level which a driver such as this must apply for a defined output load in order to reverse the charge on the relevant connecting line from the previous logic potential to the other logic potential, within one period of the data clock rate when the binary value of the signal to be transmitted changes. In systems with a high data rate (that is to say with a high data clock frequency), this current level must be matched to the system environment (line impedance, termination impedance) as a function of the data rate. Since the said current level also depends on the operating voltage and is also subject to various environmental influences, such as the temperature, it is necessary to adjust the output drivers from time to time. Similar adjustments may also be required for the reception drivers in the data interface of the RAM module.
All of the drivers that have been mentioned normally each have a pull-up branch, which is switched on in response to the one binary value of the signal to be amplified, in order to connect the output node of the driver to the “high” logic potential H, and a pull-down branch, which is switched on in response to the other binary value of the data signal, in order to connect the output node of the driver to the “low” logic potential L. The current level of a driver can be increased or decreased by increasing or decreasing the driver impedance. Because of unavoidable asymmetries in the characteristics of the pull-up and pull-down transistors, it is expedient to adjust the pull-up driver impedance and the pull-down driver impedance separately, by variation of the effective on-state impedance in the branches. This can be achieved by varying the number of parallel-connected switching transistors or by special resistive elements in the branches.
It is known for the control information for adjustment of parameters of the output drivers in the data interface of a RAM module (OCD parameters) to be transmitted from the controller via the data and strobe lines to the RAM module during an adjustment interval. The connecting branches which pass via these lines between the controller and the RAM module are referred to here as a “data channel”. The control information is transmitted in serial form as a burst of control bits at the data clock rate. One appropriate method is specified in the so-called “DDR2-JEDEC Standard for DRAMs”. This standard relates to a memory mode in which the data clock rate is twice as fast as the basic clock rate of the memory system (Double Data Rate “DDR”). The control bit burst contains 4 bits, which indicate which driver parameter (pull-up impedance or pull-down impedance) should be adjusted, and in which direction (increase by one step or reduce by one step). The adjustment is then carried out in the RAM module by means of a setting device which influences the stated parameter, by one step in the indicated direction. A test transmission of data is then sent via the output drivers of the RAM module to the controller using the parameter settings that have been applied, and the controller analyses the reception of this data. This action is repeated until the optimum settings are found for the OCD parameters.
The conditioning of the RAM module for this adjustment mode is carried out by inputting a specific bit pattern into selected cells in the mode register. Once the optimum settings of the OCD parameters have been found, these settings are locked by inputting a different specific bit pattern into the said cells in the mode register.
This known adjustment method has the disadvantage that the control bit burst sent via the data channel has a wider bandwidth the higher the data clock rate is. Since the bandwidth of the data channel is limited, there is thus a risk of the control bit burst being distorted, when the data clock rate is high, to such an extent that the binary values of the individual bits are no longer reliably identified in the RAM module.